The present invention relates to a circuit optimization system for synthesizing a circuit like CMOS or LSI on the level of individual transistors in designing the circuit.
Thanks to recent marvelous development in semiconductor device manufacturing technologies, a so-called "system-on-chip" is now prevailing in the art. That is to say, various functions of an overall system, like computer or telecommunication unit, can be incorporated into a single-chip semiconductor integrated circuit. Also, semiconductor device manufacturing technologies have lately been alternating their generations one after another at even shorter intervals than what they used to be. As a result, it has become a lot easier and much preferred to implement a system-on-chip using such downsized components. Moreover, a semiconductor chip now has to meet a multiplicity of requirements, like low power dissipation, high performance and cost reduction, either selectively or simultaneously, depending on the applications and the operating conditions of specific systems. Accordingly, in order to cope with such a wide variety of demands, multiple sets of techniques should be prepared beforehand in manufacturing a semiconductor integrated circuit.
If the number of variant semiconductor device manufacturing processes or the size of an overall system is increased, then the number of processing steps should also be increased in designing a semiconductor system. Thus, designing techniques should be innovated to reduce such an increased number of designing process steps. According to a most promising measure to reduce the number of designing process steps, circuits having an equivalent function are utilized as recyclable components irrespective of a specific semiconductor device manufacturing process.
Such recyclable functional circuits or layout components are called "hard IP's". In order to recycle these hard IP's, a variety of techniques, including layout compaction and layout synthesis, may be employed. In accordance with a layout compaction technique, the layout can be automatically modified if the design rule employed in a semiconductor device manufacturing process is changed, as disclosed in Japanese Laid-Open Publication No. 10-3491, for example. On the other hand, in accordance with a layout synthesis technique, various types of layouts are represented by respective parameters associated with individual design rules. Furthermore, if a semiconductor device manufacturing process is modified, then an optimum size of a transistor changes correspondingly. Thus, a method of combining a transistor sizing technique (see, for example, Japanese Laid-Open Publication No. 11-3973) with a layout compaction technique has also been proposed.
However, in accordance with conventional techniques for recycling hard IP's, the structure of a circuit cannot be changed. Accordingly, if a circuit structure to be recycled does not fit in with new conditions imposed by updated process technologies, then the circuit is no longer optimal.